[Libre-soc-dev] daily kan-ban update 12oct2020

Tobias Platen libre-soc at platen-software.de
Mon Oct 12 21:05:10 BST 2020

On Mon, 12 Oct 2020 12:46:22 -0700
Cole Poirier <colepoirier at gmail.com> wrote:

> Today:
> created litex/florent/ulx3s85f.py based on
> lites/florent/versa_ecp5.py, successfully completes when run as
> `./ulx3s85f.py`, `./ulx3s85f.py --build`, and loads to my 85K LUT
> ULX3S FPGA when run as `./ulx3s85f.py --load` :)
> What should I do now? Try sending commands over JTAG, openocd, gdb?
> Now, going to work on adding getopt to all of the currently hard-coded
> options in simple/issuer_verilog.py etc, making sure to test that it
> still works with this augmentation.
> Cole
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Today: updating gitlab-ci.yaml

I also found out that power-instruction-analyzer does not get checked out when running make gitupdate.

Processing dependencies for soc==0.0.1
Searching for power-instruction-analyzer
Reading https://pypi.org/simple/power-instruction-analyzer/
Couldn't find index page for 'power-instruction-analyzer' (maybe misspelled?)
Scanning index of all packages (this may take a while)
Reading https://pypi.org/simple/

Tobias Platen <libre-soc[at]platen-software[dot]de>

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