[Libre-soc-dev] daily kan-ban update 10oct2020

Cole Poirier colepoirier at gmail.com
Sun Oct 11 22:13:27 BST 2020

On Sun, Oct 11, 2020 at 1:21 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On 10/11/20, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > sim.py operational with this, below.
> i have sim.py operational but versa_ecp5.py is not.  i back-tracked to
> mid-september and that will display one line of text on the serial
> console then stop.
> with no JTAG i can't get in and test it, i'll need to get some jumper
> wires or hack up the 20 pin connector that comes with an STLINKv2.

Awesome, same here, though
`/home/colepoirier/src/litex/litex/build/sim/core/sim.c:95 Could not
find module jtagremote`, but it exists in the same directory?
Yup, sim reaches here and then seems to freeze (not respond to 'q' or
'esc') maybe I didn't wait long enough?
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.

How can I help with versa_ecp5.py? I have my stlinkv2, but I think I
have the low end one that can connect with just four pins (has 10 pins
total), not the massive complex 30+ pin one... This should work right?
I can successfully program my ulx3s85F over my stlinkv2 jtag.


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