[Libre-soc-dev] daily kan-ban update 10oct2020

Cole Poirier colepoirier at gmail.com
Sat Oct 10 22:35:23 BST 2020

New, possibly more relevant error... from yosys this time. no idea how
to go about trying to fix this.

4.6. Executing FLATTEN pass (flatten design).
<suppressed ~52 debug messages>
ERROR: Mismatch in directionality for cell port
versa_ecp5.test_issuer.int_level_i: \main_testsoc_libresoc_interrupt
<= \test_issuer.int_level_i


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