[Libre-soc-dev] daily kan-ban update 10oct2020

Cole Poirier colepoirier at gmail.com
Sat Oct 10 22:24:04 BST 2020

On Sat, Oct 10, 2020 at 2:12 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> issuer_verilog.py generates verilog according to parameters.  copy to
> litex libresoc directory.  sim.py, ls180.py, versa_ecp5.py all take
> that (same) file, and according to libresoc/core.py "variants"
> parameter (currently ls180, standard, standard32) do different "stuff"
> with that "core" (libresoc.v).
> the litex "stuff" needs different pins and different functions
> therefore back in the core (issuer_verilog.py) you need different
> options.

Super, super, helpful!! All of this really needs to be documented,
which I'm planning to do once I've figured out how the system works,
and have actually gotten it to work properly. And the HDL_workflow
page gets longer, and longer... :)


More information about the Libre-soc-dev mailing list