[Libre-soc-dev] daily kan-ban update 10oct2020

Cole Poirier colepoirier at gmail.com
Sat Oct 10 21:57:50 BST 2020


On Sat, Oct 10, 2020 at 1:53 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> On Sat, Oct 10, 2020 at 1:32 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> > you see in issuer_verilog.py, the option to enable "test_gpio"?  then
>
> No such variable test_gpio, do you mean:
>
> ```
> 20     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
> 21                          imem_ifacetype='bare_wb',
> 22                          addr_wid=48,
> 23                          mask_wid=8,
> 24                          # must leave at 64
> 25                          reg_wid=64,
> 26                          # set to 32 for instruction-memory width=32
> 27                          imem_reg_wid=64,
> 28                          # set to 32 to make data wishbone bus 32-bit
> 29                          #wb_data_wid=32,
> 30                          xics=True,
> 31                          nocore=True, # to help test coriolis2 ioring
> 32                          gpio=False, # for test purposes
>                               ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Tried changing this to 'True', I get the exact same error. What am I
doing wrong?

Cole



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