[Libre-soc-dev] daily kan-ban update 10oct2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Oct 10 21:31:43 BST 2020

On Sat, Oct 10, 2020 at 9:22 PM Cole Poirier <colepoirier at gmail.com> wrote:
> I'm trying to execute ./soc/litex/florent/versa_ecp5.py --build and
> getting a cryptic error about a missing port. Any idea what this might
> be?

have a look in issuer_verilog.py and also in issuer.py

> ```
> 4.4.3. Analyzing design hierarchy..
> Top module:  \versa_ecp5
> Used module:     \test_issuer
> ERROR: Module `test_issuer' referenced in module `versa_ecp5' in cell
> `test_issuer' does not have a port named 'gpio_wb__err'.

no gpio wishbone port.

you see in issuer_verilog.py, the option to enable "test_gpio"?  then
in issuer.py "if gpio_en add wishbone port"?  guess what that does...


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