[Libre-soc-dev] make run_sim failure

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Oct 8 22:07:12 BST 2020

On 10/8/20, Cole Poirier <colepoirier at gmail.com> wrote:
> Hi Luke,
> I've been trying to successfully compile and run the litex-libre-soc
> simulation for over a week

question: why did you waste 6 days not communicating?

that's a staggering 30% of the remaining time until the chip gets done.

if you had asked 6 days ago you would have found out 6 days ago that i
haven't had time to keep ls180soc.py and versa_ecp5.py and sim.py all
in sync and all working because i am not getting enough help from
everyone else to do so, given that i am only about 40% effective
because of this virus.

and i could have advised you, 6 days ago, of an approach on how to fix it.

i will take a look (tomorrow, which is yet another day, 8% of
available time until the deadline) and see what needs doing.


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