[Libre-soc-dev] daily kan-ban update 06oct2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Oct 8 18:24:23 BST 2020

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Thu, Oct 8, 2020 at 4:53 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> On Wed, 7 Oct 2020 22:53:40 +0100 Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > i am thinking, for fu/mmu/main_stage.py this is more like
> > loadstore1.vhdl and to add a PortInterface to it.

> > what do you think?
> That seems to be a good idea.
> I'm currently looking at the ways how I could implement that.

it's this (below).  then it *should* be a matter of examining the
fields from self.mmu and  self.dcache), wiring up the request.

according to loadstore1.vhdl - line 598, 600 and 605 (which are LD, ST
and DCBZ respectively) we set v.load and req

however at lines 689 and 701, the request is put into *both* dcache and mmu.

but, ahhh, if you look back at the FSM (when ACK_WAIT, and
OP_FETCH_FAILED), it's if the dcache request fails that you then
"activate" the mmu.

mmm... this is going to be tricky....

commit ffdfe62279fdff8c695d57ca4d8dccdd719074d4 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Oct 8 18:13:50 2020 +0100

    add incoming PortInterface to be connected to LoadStoreCompUnit

+++ b/src/soc/fu/mmu/fsm.py
@@ -21,6 +22,9 @@ class FSMMMUStage(ControlBase):
         self.p.data_i = MMUInputData(pspec)
         self.n.data_o = MMUOutputData(pspec)

+        # incoming PortInterface
+        self.pi = PortInterface("mmupi")

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