[Libre-soc-dev] daily kan-ban update 08oct2020

[Tobias Platen]

today: reading soc/src/soc/fu/mmu/*.py and thinking how to connect this to the rest of the soc.
that is definitively different from microwatt, it only has MMUInputData and MMUOutputData. 
I also handles MTSPR, MFSPR, DCBZ and TLBIE. 

On Thu, 8 Oct 2020 17:53:16 +0200
Tobias Platen <libre-soc at platen-software.de> wrote:

> On Wed, 7 Oct 2020 22:53:40 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> 
> > On 10/6/20, Tobias Platen <libre-soc at platen-software.de> wrote:
> > > On Tue, 6 Oct 2020 19:03:12 +0100
> > > Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > >
> > >> On 10/6/20, Tobias Platen <libre-soc at platen-software.de> wrote:
> > >>
> > >> >> ICache MMU unit test
> > >> > I'm currently working on that, I just did not commit my changes yet.
> > >>
> > >> ah ok excellent.
> > > First set of changes have been commited.
> > 
> > 
> > https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=dda456f48c2081793c1829cbe64d953e68eba01b
> > 
> > good catch.
> > 
> > i am thinking, for fu/mmu/main_stage.py this is more like
> > loadstore1.vhdl and to add a PortInterface to it.
> > 
> > then the LDST CompUnit sends all LDST operations to the *other*
> > CompUnit (MMU) which contains a dcache instance and an mmu.py
> > instance.
> > 
> > slightly different from how it's done in microwatt.
> > 
> > what do you think?
> That seems to be a good idea. 
> I'm currently looking at the ways how I could implement that.
> > l.
> > 
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> 
> 
> -- 
> Tobias Platen <libre-soc[at]platen-software[dot]de>
> 
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-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>