[Libre-soc-dev] question about LRU implementation

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Oct 7 04:56:58 BST 2020

On 10/7/20, whygee at f-cpu.org <whygee at f-cpu.org> wrote:
> Hello,
> I am doing some research about LRU strategies and circuits,
> so my question is : can any of you explain the methods
> used by (or intended for) the cache memories and the TLB
> selection & eviction circuits ?

not really, because i tend towards saving time (like, cutting to 10%
of "NIH" approaches favoured by other people) by grabbing known-good
working code from elsewhere, blindly and faithfully converting it, and
leave "understanding" as a retroactive activity that often happens 2
to 24 months later, with EXTENSIVE unit tests bridging between the two
in the intervening time.

this approach means that it is "safe" to proceed even on a massive
project even with very little working knowledge of the underlying
algorithms, avoiding both decision paralysis and NIH syndrome.

it does however mean that ordinarily it would be possible to answer
your question sonewhere in about 1 years' time.

luckily for you however i did a comparative analysis of PLRU
algorithms based it has to be said on near zero knowledge and you can
find it on the openpower hdl cores archive.


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