[Libre-soc-dev] daily kan-ban update 06oct2020

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Oct 6, 2020 at 8:00 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
>
> On Tue, 6 Oct 2020 19:03:12 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>
> > On 10/6/20, Tobias Platen <libre-soc at platen-software.de> wrote:
> >
> > >> ICache MMU unit test
> > > I'm currently working on that, I just did not commit my changes yet.
> >
> > ah ok excellent.
> First set of changes have been commited.

ok good stuff.  quick review

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 2f089c91..e0fadc82 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -119,6 +119,25 @@ class PortInterface(RecordObject):

+ self.mmu_done          = Signal()

not sure about this one yet.  might be needed.  leave it in for now.


+        self.mmu_err           = Signal()
+        self.mmu_invalid       = Signal()
+        self.mmu_badtree       = Signal()
+        self.mmu_segerr        = Signal()
+        self.mmu_perm_error    = Signal()
+        self.mmu_rc_error      = Signal()

ok - these can go (be deleted / removed) because they're part of the
LDSTException (which i added this afternoon)


+        self.mmu_sprval        = Signal(64)

this can go (be deleted / removed) because we're not going to pass
SPRs through PortInterface.  SPR modifications are handled by the
CompUnit itself.


+        # dcache
+        self.ldst_error        = Signal()
+        ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
+        self.cache_paradox     = Signal()

not sure about these.  my feeling is that they're not going to be
passed through PortInterface itself, but they might.  have to see:
leave them in for now.

l.