[Libre-soc-dev] Litex-OPENTitan clarification

Cole Poirier colepoirier at gmail.com
Mon Oct 5 17:38:25 BST 2020

On Sun, Oct 4, 2020 at 7:28 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On 10/5/20, Cole Poirier <colepoirier at gmail.com> wrote:
> > On Sun, Oct 4, 2020 at 6:52 PM Luke Kenneth Casson Leighton
> > <lkcl at lkcl.net> wrote:
> actually it's not so bad.  the actual pinmux and associated control
> regs is what is missing entirely from open source except in opentitan.
> reason: nobody has bern doing ASICs until recently, and FPGAs well um
> you just reconfigure the bitstream and compile in different
> peripherals, what the hell would you need to waste LUTs on a pinmux
> for??

Ah, that's a fantastic, and fascinating explanation.

> >> what we *might* be able to do is use the devicetree generation etc.
> >> aspect of opentitan.
> this as predicted is horseshit.

Surprise, surprise...

> if over the past 30 years there are 50,000 unique I2C and SPI
> peripheral ICs
> copyright law.

Hmm sounds interesting but I don't understand fully, will just ask for
clarification on our call today.

> don't know.  probably.  too much to decide there.  too much distraction.


> > So, to clarify, you want the nmigen-litex to be discussed after the
> > Euro 2 DEC tapeout?
> yes.

Ok, makes sense.

> > Additionally, what are our responsibilities between 30 OCT code freeze
> > and 2 DEC tapeout?
> testing. simulation. mmu. dcache. icache.  jtag.

... I thought we couldn't add the mmu/icache/dcache if they aren't
complete by 30 OCT?


More information about the Libre-soc-dev mailing list