[Libre-soc-dev] Litex-OPENTitan clarification

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Oct 3 12:13:16 BST 2020

On Sat, Oct 3, 2020 at 6:30 AM Cole Poirier <colepoirier at gmail.com> wrote:

> magical thing, it would be foolish for me to *actually* pursue this. So
> fascinating, and delightful really.


> Have you outlined our direct, based-on-our-needs python version on the wiki
> or a bug report?

check the creation date on these:

> Or is this something that is deferred until our bugzilla
> review after the code freeze deadline?

realistically, it's "after".

> > if the OpenTITAN / lowRISC team had consulted us, sought our input,
> > and looked for ways to collaborate, i would not be asking that
> > question.
> >
> Am I correct in recalling that they used your pinmix work?

no - they saw the announcement that i'd created a BSV one for the IIT
Madras Team, and went, "hmmm, we will do this too".  they _could_ have
gone "we will do this too... *and we will include the IIT Madras Team,
etc. etc. and basically make something like litex for EVERYONE to use
not just us".

iitex is... very close to being the perfect "system chip generator"
except it is really annoying that, being based on migen, you make one
single mistake and it can be hours to days wasted because migen has
*zero* typechecking / safety features.

> Besides the work on icache.py and the related wb_get work, what else can I
> be working on that would be helpful?

unit tests for mmu, icache and dcache.  getting to be comfortable with
it, if we're going to put it into the chip for Dec 2 it needs some
serious focus.

adding a test of IO pins to debug/test/test_jtag_tap.py.  i *think*
these are "standard-defined JTAG behaviour".  need to work out the
code (or find IEEE JTAG documentation)

some commands here:

and here you can see the Muxes being created:


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