[Libre-soc-dev] setvl encoding ideas & planning ahead for bigger register files for future processors

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Nov 30 20:21:19 GMT 2020

jacob my head is spinning from doing Compressed for nearly 10 hours
straight without a break, since i woke up.

i will have to come back to this one, on the meantime can you raise a
bugreport if one doesnt exist), link it on a stub page
openpower/sv/setvl.mdwn which i will create just after writing this.

On 11/30/20, Jacob Lifshay <programmerjake at gmail.com> wrote:

> Now that I think of it, setvli can share VL and MVL fields because
> practically speaking they will always be identical, so there is waay less
> pressure than originally anticipated. I guess we could then share encodings
> by having RS=0 mean setvli and RS!=0 mean setvl.

briefly: this is close to the rationale behind the 12bit encoding on
the SVP64.  it means a full Major opcode is not taken up, it embeds
(kinda) into EXT31 or possibly EXT19 with a similar trick to how isel
and crops work: taking up an *area* of XO subselector (a 16 or 32 long
column) rather than individual entries of the 1024 possibilities of


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