[Libre-soc-dev] setvl encoding ideas & planning ahead for bigger register files for future processors
programmerjake at gmail.com
Mon Nov 30 11:39:52 GMT 2020
I thought of something: what if we required MVL to be limited to a few
special values: 0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 24, 32, 48, 64? That
would take 4 bits to encode allowing the extra bits to be used to encode VL
in a similar way using 5 bits (for the setvli instruction, setvl just has a
register field there).
If there are extra bits (which I'm hoping is the case), they would be
reserved (illegal instruction trap if non-zero).
Future processors can have them encode a number of bits that all register
fields are shifted left in all following instructions. This allows easy
extension of the size of the int and fp register files to 256/512/1024/...
registers instead of the 128 we currently have. registers are renumbered as
part of setting the shift avoiding the need to move values around.
e.g. if the shift is set to 3, then:
addi r5, r63, 1234
addi r40, r508, 1234
because 40 == 5 << 3 and 508 == 63 << 3
this can be implemented at the hw level by always shifting register fields
left by the max supported amount and just reducing the amount that register
numbers increment by during SV vector decoding (and anything else that
requires adjacent register numbers at the ISA-level) when the sw-visible
shift amount is increased.
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