[Libre-soc-dev] results of phone call about simple-v prefix
richard.wilbur at gmail.com
Sat Nov 28 20:43:57 GMT 2020
> On Nov 28, 2020, at 01:19, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> i will be sad in a Top Gear Jeremy Clarkson way to see SV-P64 unable
> to do single instruction self-contained predicated full arbitrary
> vectorisation of all and any scalar instructions.
> my favourite is full twin-predicated vectorised LD and ST. SV-P64
> LD/ST is the "dream" bucketlist instruction that every ISA wishes they
> had then regrets efforts to jam it into a scalar ISA. ARM, POWER,
> MIPS, x86, they've all tried it on and had to backpedal.
> SV-P64 LD/ST is *accident and incidental* provision of a
> context-switch and function call "dream instruction" that can place
> context-sensitive parts of a full and entire register file onto and
> off of the stack in *one* instruction.
> the predicate register acts as the mask that indicates which registers
> are relevant to the function call and need pushing or popping on the
> stack. likewise for context-switching.
> and it wasn't even planned to be deliberately added, it just happened
> to fall out of the prefixing!
I think I feel your pain, Luke! That is a particularly beautiful thing to have in your architecture—and particularly heart-breaking to lose. Especially in light of context-switching efficiency and the hoops other architectures have jumped through to achieve it! I am thinking of SPARC with register windows (also on i960, IA_64, 29k) into a built-in register stack[*] versus separate push/pop per register.
Looks like I need to read up in the list archives to understand why we would consider dropping those instructions. (Hints of where to start reading gratefully accepted.)
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