[Libre-soc-dev] compressed instructions state requirements

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Nov 25 16:57:10 GMT 2020

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Wed, Nov 25, 2020 at 2:06 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Tue, Nov 24, 2020 at 9:07 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> > The way I'm envisioning it, SVP64 instructions share the PowerISA v3.1
> > prefix encoding space with PowerISA v3.1 64-bit instructions (more than
> > half that space is available),

another reason to scratch this idea is that it mixes up the 1st-level
length/mode identification pipeline stage with the 2nd-level
(otherwise formerly completely independent and parallel)
instruction-decode phase (PowerDecoder2).

it really *really* has to be kept to as few gates as possible to
perform that length-mode identification.


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