[Libre-soc-dev] efficient decoding algorithm for variable-length instructions

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Nov 25 12:52:49 GMT 2020

On Wed, Nov 25, 2020 at 6:06 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> I wrote out the following decoding algorithm for variable-length instructions:
> https://libre-soc.org/openpower/sv/16_bit_compressed/decoding/
> It uses the 16/32/48/64-bit encoding that I proposed in earlier
> emails. It has a circuit depth of O(log N) for a decoder that can
> decode N instructions per cycle.


just to check: https://libre-soc.org/openpower/sv/16_bit_compressed/

    "Demo of encoding that's backward-compatible with PowerISA v3.1 in
both LE and BE mode"

i believe we determined yesterday that this is not true?  that 16/48
(as i intuited/suspected" prevents and prohibits inter-mingling of
v3.0B, v3.1B and 16/48-bit prefixed instructions without additional
state (such as a VLE-like 64k page marker bit)?


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