[Libre-soc-dev] daily kan-ban update 18nov2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Nov 19 01:28:05 GMT 2020
On Wed, Nov 18, 2020 at 7:58 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> yesterday and today: reading dcache.py and loadstore1.vhdl,
> deciding which changes may be needed in mmu.py or dcache.py,
> looking for ways to report change of DSISR and DAR to CPU.
yeah this is complicated. the LD/ST CompUnit is not a pipeline (not
managed by MultiCompUnit), it's a hard-coded FSM that has the same API
*as* MultiCompUnit. this so that early receipt of RA and RB can do
Address-Generation and trigger an early memory-check whilst still
waiting for RT.
that means that DSISR and DAR need to be passed through the LDST
CompUnit to the MMU which works in *conjunction* with LDST CompUnit
rather than being "the one unit" as is the case in microwatt.
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