[Libre-soc-dev] 3d gpu business plan

Lauri Kasanen cand at gmx.com
Wed Dec 30 18:40:12 GMT 2020

On Wed, 30 Dec 2020 12:25:39 +0000
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> just like Samsung and Allwinner they have multiple overlapping teams.

I know.

> how many pins does it have, and what's the
> maximum processor speed?  based on that: is it suited to anything
> remotely similar to what we're trying to do?

That's not related to what I wrote at all. I wrote about Mediatek/etc
wanting an ESP replacement, not about ESP being a threat to LibreSoc.

> however what you are missing is that
> there's been several RISC-V cores already gone into mass-production.
> Trinamic was one of the first.  Western Digital was another.  NVidia
> *might* have already done so.

Again I know. Am I writing too tersely or in a confusing way?

> OpenPOWER - the ISA itself - is total overkill for them.  an OpenPOWER
> ISA decoder alone is larger than the entire RISC core used in that
> type of processor.  they would be utterly shooting themselves in the
> foot to use it, because the die area would be increased so greatly
> that it would knock the price up by a margin so high that it would
> become unprofitable against their *own* current product.

Good answer! Now, this is the meat. This, enumerating each significant
threat, is what should be listed in the business plan. It shows we have
considered the threats widely, and communicated them to potential
investors in a way they can understand.

Something like this:

The open development model and freely licensed end product would allow
a skilled competitor to copy us before our product is out. However,
given the startup costs involved, they would only do so for highly
lucrative markets. Otherwise they would copy the product only once it
has proven successful, giving us a lead time of several years.

The markets where core licensing cost is significant, and volumes
sufficient are roughly:
- ESP-like internet-of-things
- digital set-top box/mini console
- low-end phones

Our core is expected to have a die area of XX mm2 at XX nm. The ESP
series is around 0.15 mm2 at 90nm; each mm2 on older nodes costs on the
order of 0.05$ (0.25$ for 5nm) for the wafer alone. For ESP-like
applications, the core being free would not offset the larger area.

Set-top-boxes or mini consoles would be a viable target for them only
once driver support existed. Copying us in-progress would show such
high confidence in us that they'd be better off investing in us

Low-end phones rely on the modem being integrated. Integration work may
only begin in earnest once the core is relatively far along, losing
them some time edge; and before they have the core and modem
integrated, they can't assess the total power usage, necessary for this

- Lauri

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