[Libre-soc-dev] svp64 questions: variable parallelism vs predictability

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Dec 26 06:36:02 GMT 2020

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On Sat, Dec 26, 2020 at 3:28 AM Alexandre Oliva <oliva at gnu.org> wrote:
> Should I raise them here, or in bugzilla (213?)
> One issue in my mind is parallelism and ordering guarantees of the
> specification, considering that the amount of parallelism may vary.
> Consider:
>   setvli 45  ; set vector length to 45
>   mv 39, 36  ; copy 45 registers from r36 on to r39 on

allow me to go through it [in a logical reasoning way rather than
giving a yes-no answer]

as it is on top of a scalar register file this is as if the following
had occurred:

 mv 39, 36
 mv 40, 37
 mv 41, 38
 mv 42, 39
 mv 43, 40

the requirement is to provide the expected behaviour as if those
instructions had been issued literally in the instruction stream.
SV's for-loop is simply a "compactification" of such a program.

if this were simply a scalar processor you would not be asking the
question, because it would be obvious that no scalar processor would
be accepted into the marketplace if it could not keep the order
correct when issued with the above (long list of 45) mv operations.

SV is no different.  the behaviour is *required* to be thought of "as
if a scalar processor had been given multple instructions" because the
"Vector" for-loop is quite literally a Sub-Program-Counter.

instructions issued by the Program Counter have strict ordering
guarantees: why would the Sub-Program-Counter (0..VL-1) be treated any


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