Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Dec 22 19:29:53 GMT 2020
On Tuesday, December 22, 2020, Cole Poirier <colepoirier at gmail.com> wrote:
> It's almost as if the original designers and subsequent contributors
> to the POWER ISA over the past 25 years knew what they were doing!
they probably did, given the success it had in the PS3.
however: look at the instruction count of VSX. sonewhere around 700 i
think. this because it is SIMD-with-a-smidgen-of-Vector ops.
so the sigarch "SIMD Considered Harmful" article definitely applies.
now look at RVV. the Vector ISA *more than doubles* the instruction count
yet, to get a Vector ISA that is a peer of RVV we add... 5 to 8
instructions to an OpenPOWER *Scalar* ISA?
the point being: the exact same argument that was applied *by the
developers of RVV* to SIMD apply just as equally to the opcode
proliferation that is embedded into RVV itself, although RVV is less
this is the point of the abstraction prefixing in SV: don't create separate
vector instructions, because you're only duplicating the scalar ISA in
about 95% of cases.
underneath, SV is a handful, like hanging on to a pissed-off bunch of
howling wolves with their tails knotted together, but hey.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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