Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Dec 21 13:54:55 GMT 2020
i've added the following section below to indicate that in the future - not
now - extending beyond 128 registers will be discussed.
when speaking with another experienced project manager, one with silicon
experience, an associate asked, "what is the number one cause of failures
in ASIC dedign that you have witnessed?"
the answer was abundantly clear: *changing the design when deadlines
over the past 24 months there has been too much preparation, thought and
analysis gone into the design to make radical changes to the naming.
its purpose was to extend the regfile in the future: there is an
alternative that keeps the existing scheme on which all analysis and design
of the past 24 months is based.
i consider the alternative naming scheme discussion now closed until after
the first implementations of binutils, simulator and HDL are completed and
we enter "reevaluation" phase.
With the way that EXTRA fields are defined and applied to register fields,
future versions of SV may involve 256 or greater registers. To accommodate
256 registers, numbering of Vectors will simply shift up by one bit,
without requiring additional prefix bits. Backwards binary compatibility
may be achieved with a PCR bit (Program Compatibility Register). Beyond
this, further discussion is out of scope for this version of svp64.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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