[Libre-soc-dev] svp64

Jacob Lifshay programmerjake at gmail.com
Sun Dec 20 06:10:01 GMT 2020

On Fri, Dec 18, 2020, 16:59 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> https://libre-soc.org/openpower/sv/sprs/
> found the relevant section and cut/pasted it.
> it's not just MVL and VL that need to go into the SPR, it's the srcoffs
> (and for twin pred the destoffs) as well.
> so that was why 32 bits is needed.  storing the srcoffs, destoffs and
> subvloffs which are the indices of the current loop for i in range(VL) is
> what allows re-entrancy and hugely reduces latency as well as not messing
> with LDST if there are pagefaults.
> basically srcoffs destoffs subvloffs are all parts of the *Program Counter*
> and need to be respected and treated as such.
> by a jammy fluke you can see there are 4 bits spare.  it is not
> unreasonable to reserve these to extend to 0 to 64 but if trying to go to
> 128 or 256 that is not going to fit into 32 bits.  just bear that in mind.
>  it will need an extra SPR.
> 32 bits because it starts to get quite a lot, one for user space one for
> supervisor one for hypervisor.  remember this is an extension of the PC so
> have to take care.
> construction of immediate constants into 32 bits is 3 instructions.  64
> bits requires 6. to be avoided.

You basically never need to fill in the sprs from immediates through mtspr
... they are set by setvl[i] and by normal control flow. you basically only
need mtspr for context switch, where your loading values from memory, not

That is assuming that SVP64 is how SV will be used for now, since the
special compressed/vblock forms have the issues with 16/48-bit instructions
and are probably not going to be in the initial implementation.

> also the Twin Pred SUBVL concept whilst a good one (redundant as it turns
> out) would require an extra 2 bits for a destsubvloffs and you can see if
> we expand VL to 7 bit it is not going to fit.

we need separate src subvl for swizzle ops (at least the dedicated ones),
otherwise the cpu won't know how big the src subvl is, since it doesn't
match dest subvl. basically, swizzle is how you transfer vector data
between vectors of different subvl.


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