[Libre-soc-dev] [Libre-soc-misc] How not to design instruction sets
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Dec 18 04:13:44 GMT 2020
On Monday, December 14, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On 12/14/20, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>> On 12/14/20, Jacob Lifshay <programmerjake at gmail.com> wrote:
>>> On Mon, Dec 14, 2020, 11:43 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
>>>> On 12/14/20, Jacob Lifshay <programmerjake at gmail.com> wrote:
>>>> > I found this on the RISC-V mailing lists, looks interesting:
>>>> > https://player.vimeo.com/video/450406346
the "stuff" referred to by the hardware designer that had "already been
done" is the address overlap detection in the multi way load store merger.
we call that L0CacheBuffer.
to ensure that simultaneous LDs or STs may be merged into a single wide
cache line request it is necessary to perform address conflict detection.
this is a triangular comparison and oh look conflictd is a triangular
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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