Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Dec 17 22:43:53 GMT 2020
On Thursday, December 17, 2020, Jacob Lifshay <programmerjake at gmail.com>
> On Wed, Dec 16, 2020, 14:54 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
>> On Wednesday, December 16, 2020, Luke Kenneth Casson Leighton <
>> lkcl at lkcl.net>
>> > ok summary changes this afternoon:
>> > * made a note that the 24 bits as all zeros ahould be "SV quiescent".
>> this would allow for standard v3.1B to run "as usual" including *sigh*
>> you mentioned something about nop and how all 0s in the 24 bits "will not
>> work". if that is not the case then i would like svp64 to be changed so
>> that it does. e.g. the EXTRA2/3 fields if zero mean "scalar behaviour of
>> registers" and so on.
> What I originally thought you meant is that you wanted all 0s to be an
> instruction you could run to detect if SV mode is enabled and trap
> otherwise, you can just use a SV prefixed
> `ori r0, r0, 0` (aka nop) for that.
ahh yehyeh no not a nop. v3.1B compatibility (all of it).
> Note that all 0s in the suffix is specifically reserved since prefixing an
> implementation-defined or illegal instruction doesn't change it's
> implementation-defined/illegal state.
relative pronoun "its".
yeh no not change the bits 6 and 9 (whatever) from their constant 1s.
ah doh. constant 1s... it's not going to be all zeros after all, is it?
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