[Libre-soc-dev] svp64 and opcode_regs_deduped

Jacob Lifshay programmerjake at gmail.com
Wed Dec 16 03:28:50 GMT 2020

I think we'll need to go through the OpenPower base instructions and
manually categorize them, since the categories in opcode_regs_deduped
have some issues.

rlwimi is a good example: it is listed as 2R-1W-CRo but only has 2
register fields but also can't really be a twin-predicated instruction
since the first register is both read and written. I think the SVP64
encoding for it should also have just 2 register fields.

So, the encoding break-down needs to be based on both which
inputs/outputs instructions have as well as how many register fields
each instruction has. This is really starting to remind me of x86 with
all its weird and "wonderful" instructions -- too bad RISC-V's not a
good option any more, it is much cleaner.


More information about the Libre-soc-dev mailing list