[Libre-soc-dev] v3.1B prefix
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Dec 13 22:17:03 GMT 2020
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sun, Dec 13, 2020 at 9:52 PM Alexandre Oliva <oliva at gnu.org> wrote:
> On Dec 8, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > On 12/8/20, Alexandre Oliva <oliva at gnu.org> wrote:
> >> On Dec 7, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> >>> i did find it odd that there's no 16-bit imm instructions,
> >> Sorry, I failed to mention that they're not implemented yet.
> > lol that would do it. addi is the higher end of the opcodes used.
> > although not being able to use it unless already in 16bit mode, this
> > is very inconvenient.
> I'm trying to implement the remaining opcodes now, but getting all
> confused by the mismatches between the bit widths and range of values
> supposed to be encoded:
> | 0 | 1 | 2 | 3 4 | | 567.8 | 9ab | cde | f |
> | 1 | 1 | 1 | i2 | | 001.0 | RA!=0| imm | 1 | addis
> | 1 | i2 | | 010.0 | RA!=0| imm | 1 | addi
> * addi is EXTS(i2||imm) to give a 4-bit range -8 to +7
> * addis is EXTS(i2||imm||000) to give a 11-bit range -1024 to +1023 in increments of 8
> I suppose the bullets are lagging behind encoding updates, because:
yes. i had to jig them about. the descriptions are out-of-date.
> If these were to be used the way I would conceive of them, the ranges
> would be complementary, so that a pair of these insns could encode 12
not bad, for so few bits, ehn?
> | 1 | 0 | i2 | | 010.1 | RA | imm | 1 | cmpdi
> * all others are EXTS(i2||imm) to give a 7-bit range -128 to +127 (further for LD/ST due to word/dword-alignment)
> - I count 6 bits, -32..+31. It would take 8-bits to encode -128..+127.
> I guess at this point none of this really matters, but you were so
> interested in the compressor estimates for 16-imm that I figured I'd
> implement them, but... tough.
well, we are likely down the road to still need to put 16-bit
instructions and an 11-bit SV Prefix together so as to create a 32-bit
Vector-only ISA subset. this will be the only way we will be able to
then do double-swizzled operations without having massive
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