# [Libre-soc-dev] twin predication and svp64

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Dec 11 16:30:54 GMT 2020

```i forgot: if we are going to have a discussion about twin predication, then
the pseudo-code of how it's implemented needs to be kept in mind.  that is
here:
https://libre-soc.org/simple_v_extension/appendix/#tpred

get_pred_val() will obtain either the predicate as bits *OR* it will get
"all 1s" in the case where predication is not applicable.  in the case of
twin-predication this is on *both* src *and* dest.

zeroing is *not* activated / relevant in SV Prefix because we simply do not
have room.  remember that the pseudocode below is the *FULL* version of
Simple-V, where SV-Prefix is a *SUBSET* and we just have to live with
that.  annoyingly.

function op_mv(rd, rs) # MV not VMV!
rd = int_csr[rd].active ? int_csr[rd].regidx : rd;
rs = int_csr[rs].active ? int_csr[rs].regidx : rs;
ps, zerosrc = get_pred_val(FALSE, rs); # predication on src
pd, zerodst = get_pred_val(FALSE, rd); # ... AND on dest
for (int i = 0, int j = 0; i < VL && j < VL):
if (int_csr[rs].isvec && !zerosrc) while (!(ps & 1<<i)) i++;
if (int_csr[rd].isvec && !zerodst) while (!(pd & 1<<j)) j++;
if ((pd & 1<<j))
if ((pd & 1<<j))
sourcedata = ireg[rs+i];
else
sourcedata = 0
ireg[rd+j] <= sourcedata # or an operation, e.g. extsw etc.
else if (zerodst)
ireg[rd+j] <= 0
if (int_csr[rs].isvec)
i++;
if (int_csr[rd].isvec)
j++;
else
if ((pd & 1<<j))
break;
```