[Libre-soc-dev] twin predication and svp64

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Dec 11 05:18:56 GMT 2020

j remember about learning the microarchitecture.

decode phase can read regfile numbers out of the insn but it cannot
read the regfile contents.  issue phase likewise. scoreboard likewise.

this includes predicates which are just regs.

only hazard-free regs can be read or written *and that includes predicates*

nice thing about CRs as predicates is: one CR per element and they are small.

1st implementation 1<<r3 may have to be issued as bits anyway and
optimise later.

short VLs this will be fine.


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