[Libre-soc-dev] Hardware-accelerated specialized instructions
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Dec 11 00:37:23 GMT 2020
On 12/11/20, Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Thu, Dec 10, 2020, 16:14 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
>> you make a hardware triangle fill unit like Jeff did, it's not going
>> to do multiplication, is it?
> it might, since the per-pixel function is just a vec4 dot product followed
> by a reciprocal and a pile of mul-adds.
aw gad, that's funny. i was wondering if i should pick a completely
> actually, I'm pretty sure your wrong here. for 256-bit AES, the key
> schedule changes but each of the actual encryption steps still do the exact
> same 128-bit block operation.
mmm... the S-box yes, that is just a bunch of byte level independent
operations. likewise XOR is bitlevel independent, no intermixing
if 256 bit Rijndael *genuinely* does no mixing between bytes across 2
sets of 128 bit blocks that is extremely poor design. consequently i
have difficulty believing it, although most of my work back in 2002-4
focussed on Rijndael 128, so it's been a while.
my point was to try to pick another example instruction (any
instruction) that had specialist targetted uses but was a not
insignificant block of silicon.
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