[Libre-soc-dev] new svp64 page
colepoirier at gmail.com
Thu Dec 10 22:22:32 GMT 2020
On Thursday, December 10, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> not quite, this was the original design intent by the designers of
> the microwatt team, by having huge amounts of knowledge of the
> OpenPOWER ISA, worked out that it is inherently designed around
> this is in the CSV File columns (decode1.vhdl)
> there *is* only one ADD operation.
> inversion of A, inversion of output, setting carry to 0, 1 or XER.CA,
> and post-processing to generate CR0, these are all things that fall
> into the category you identify.
> they are all already part of an OpenPOWER scalar implementation.
> with SV i am trying to keep the actual vectorisation as a
> "stratification" on *top* of a scalar ISA. or, more to the point:
> this is a fundamental core design principle
> if we need Vector Average, the principle is: add it as a scalar opcode
> and then AUTOMATICALLY you get a vector version because SV applies to
> aaaaalll arithmetic operations.
> if saturating scalar add had already been added to v3.0B scalar ops we
> would not be discussing how to add saturation: we would be twiddling
> our thumbs with that crossed off the list because a VL loop would be
> applied to it, yawn, job done.
Ah ok, I think I may be confusing specialized scalar op code design
(ASIP-like??) with the auto vectorization or SIMD-fication SV provides.
I’ll start a new thread so I don’t take this one of the topic of SV.
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