[Libre-soc-dev] Coloquinte legalizer failure
staf at fibraservi.eu
Sat Dec 5 14:22:35 GMT 2020
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Luke Kenneth Casson Leighton schreef op za 05-12-2020 om 14:07 [+0000]:
> On 12/5/20, Staf Verhaegen <
> staf at fibraservi.eu
> > wrote:
> > > however to do even a "dummy" P&R a dummy (phantom) cell that can
> > > be
> > > placed is needed, isn't it?
> > Yes, but you should be able to design RTL without needing to do
> > P&R.
> the whole idea is to help JP, who is overloaded, to eliminate many of
> the early issues (ones that are related to placing *anything*,
> regardless of layout, not ones specific to a specific PDK)
I think it is more efficient to just give RTL and let him handle the
P&R fully than trying to help him in P&R. I think it will take more
overhead to stay in sync and finding out what you actually did.
Put JP in CC so he can shime in if he feels like it.
> i would greatly prefer to use the standard sram Instance that verilog
> expects, and to check that the simulated instance created by
> *unmodified* verilator, unmodified litex, unmodified migen, has the
> exact characteristics and size required.
OK, but then you need to make sure that the litex model matches fully
with the replaced yosys block model.
I have Verilog/VHDL simulation models of the SRAM, they could be easily
translated in litex or nmigen simulation models.
> when yosys is applied there and the cell is substituted.
> does that sound reasonable?
That could work but don't have enough yosys hacking experience to know
how easy/difficult it is. I'm afraid you will need to find out by
actually doing it.
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