[Libre-soc-dev] Coloquinte legalizer failure
staf at fibraservi.eu
Sat Dec 5 09:50:47 GMT 2020
Luke Kenneth Casson Leighton schreef op za 05-12-2020 om 01:18 [+0000]:
> On 12/5/20, Cole Poirier <colepoirier at gmail.com> wrote:
> because part of the layout is under NDA *he cannot provide it to
> us*,only to Jean-Paul, and Jean-Paul, also under NDA, cannot provide
You don't need the layout in order to be able to do the synthesis. You
will get the Verilog model of the SRAM block so also the input and
output signals of the block. I already gave the interface of the block
in bug 502.
I think the main question is that you do the mapping to the real block
already in (n)migen/litex using Instance or you try to do it in a
custom yosys script. The former does guarantee that you use the right
interface but I don't know the impact on your simulation flow. The
latter may cause problems if the interface to the memory block changes
in generated Verilog/ilang code.
In the long term there shouuld be a SRAM compiler allowing to generate
block of different sizes. This should then also be integrated so you
have a `memory_flexmem` command as you now have `memory_bram`.
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