[Libre-soc-dev] Coloquinte legalizer failure
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Dec 5 01:18:29 GMT 2020
On 12/5/20, Cole Poirier <colepoirier at gmail.com> wrote:
> "converts the multi-port $mem memory cells into block ram instances.
this requires that we have an SRAM cell... and that is exactly what we
do not have.
to make the "match" mentioned in that man page we require the cell
library that contains the "schematic" version and corresponding
yosys searches for the schematic version, and inserts "success" into
the netlist such that P&R knows what to pick, later.
P&R goes, "ah ha, i was told that for this thing i must pick this
physical cell then connect it up".
the entirety of ASIC development is done like this.
and right now the best "match" is: DFFs because there *is* no SRAM
cell library and consequently the next best match is "the cell library
bottom line: no SRAM cell library, no point trying to tell yosys to
match against something that is guaranteed to fail because it doesn't
Staf is going to design a 4096 byte 64bit wide SRAM Cell for us.
he is still working on it
because part of the layout is under NDA *he cannot provide it to us*,
only to Jean-Paul, and Jean-Paul, also under NDA, cannot provide it
clearly this is less than ideal, and we need a cleanroom
implementation *even of the Phantom Cell* despite the fact that it
will never get taped out because the phantom is deemed to reveal too
much information about the Foundry PDK.
deep and lasting joy all round.
thus we need workarounds and or to decide whether this is tolerable or not.
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