[Libre-soc-dev] daily kan-ban update 26 aug 2020

whygee at f-cpu.org whygee at f-cpu.org
Thu Aug 27 00:20:45 BST 2020

Hello list,

I'm not a nmigen practitioner but may I suggest VHDL newbies
to look at some reference books ? Those written by Ashenden are
usually very good and help make sense of the otherwordly syntax.
The VHDL semantic is unusual to "software coders" but it's
tightly defined and every bit has a meaning.
This would explain why for example for...loop and for...generate
are different and where/how to use them.

And Cole, once you've done the translation,
you could make a "Rosetta stone" to compare the code
of the same circuit in the two language, so it could
help others :-)

On 2020-08-26 22:02, Cole Poirier wrote:
> On Wed, Aug 26, 2020 at 1:01 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
>> everything in the reset block you delete it and add "reset=x" to the
>> appropriate signal.
> Aha! That's really cool. Thank you.
> Cole

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