[Libre-soc-dev] Div bugs
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Aug 26 00:47:25 BST 2020
On Tuesday, August 25, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Tue, Aug 25, 2020 at 9:48 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> > On Tuesday, August 25, 2020, Jacob Lifshay <programmerjake at gmail.com>
> > > On Tue, Aug 25, 2020, 07:08 Luke Kenneth Casson Leighton <
> lkcl at lkcl.net>
> > > wrote:
> > >
> > > > change of topic: jacob the DIV FSM is not producing correct output
> > > > needs some high priority attention. the incorrect output means i
> > > > test anything on the FPGA because the DIV pipe is way too large.
> > >
> > >
> > > I'm planning on working on that today
> > thanks jacob. i added an example test case at the top of the div unit
> I fixed it.
> I also found another case where the python instruction
> simulator is wrong
> -- all of the FSM, power-instruction-analyzer, and
> what I expect from reading the instruction description agree:
> def case_divw_regression(self):
> # simulator is wrong, FSM and power-instruction-analyzer are
> both correct
> lst = [f"divw 0, 1, 2"]
> initial_regs =  * 32
> initial_regs = 0x2
> initial_regs = 0x80000000
> with Program(lst, bigendian) as prog:
> self.add_case(prog, initial_regs)
> the correct result is 0xC0000000, the simulator gives 0x40000000
that iiiis... not detecting that the number is negative, i bet.
0x8000_0000 is the -ve limit.
> I'll leave that up to you to fix
need some more cases, just to be sure.
i suspect divd is wrong for 0x8000_0000_0000_0000 as well.
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