[Libre-soc-dev] [OpenPOWER-HDL-Cores] bug in libre-soc "modsd" and possibly in microwatt as well

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Aug 23 14:55:06 BST 2020

On Sun, Aug 23, 2020 at 12:51 PM Paul Mackerras <paulus at ozlabs.org> wrote:

> I looked through the log of a simulation of microwatt running 1.bin.
> I see a value of 0x7fffffff in r0 at that instruction, not 0xff.  (In
> fact the 0x7fffffff is the value initially loaded into r0 at the
> beginning of the instruction sequence.)

paul, i should clarify: aside from identifying that there's a
discrepancy between ghdl sim on 1.bin and litex sim of 1.bin (which is
useful), my question was more direct: what does divider.vhdl produce
when ra=0x7fff_ffff_ffff_ffff and rb=0xff

so i decided, ehn what the heck, i've been staring at vhdl for long
enough, i should be able to write it (w00t! success!)

divider_tb.vhdl:457:9:@12101130ns:(report note): modsd expected
000000000000007F got 000000000000007F

which now leaves me *really* confused because in that debug int
regfile dump you can clearly see r0 == 0xff not 0x7fff_ffff yet the
answer being returned in r17 is "0x1".

this leads me to suspect that there's something wrong with the DMI FSM
i created.


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