[Libre-soc-dev] daily kan-ban update 17aug2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Aug 17 19:56:48 BST 2020


* modified litex sim.py to print out debug register / pc log information in
a selective range only
* used that to track down an obscure bug in the PowerISA "cmp"

turns out that we have been ignoring the "L" field which 32bit sign-extends
the number(s) being compared.   memtest on litex sim of DDR3 now oasses.

unfortunately even after fixing this bug, litex ecp5 FPGA *still* gets
corrupted data on Memtest.

the next "trick" to try is to put a 64 to 32 bit converter in front of the
libresoc core... in nmigen.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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