[Libre-soc-dev] litex ecp5 progress, regfile-compunit arbiter needed.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Aug 16 00:53:35 BST 2020
On Saturday, August 15, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> what is needed, if the regfile output is to be delayed by one clock, is
> that the "REQUEST" has to be switched off on one clock cycle, but in that
> same cycle the regfile "enable" is still sent, and a FSM keeps track of the
> fact that the "GO_READ" must be sent on the *next* cycle.
sorted on Read, works well. i suspect that a similar trick is needed on
"write" as well, to guarantee that data is actually committed to the
regfile before allowing the CompUnit to end its "management" role.
> interestingly this should allow FPGA BRAM to be used.
it did. reducing the number of LUT4s by 2,000 in the process.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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