[Libre-soc-dev] ASIC/FPGA discrepancies (was Re: daily kan-ban update 12aug2020)

Lauri Kasanen cand at gmx.com
Thu Aug 13 06:51:49 BST 2020

On Wed, 12 Aug 2020 16:11:20 -0700
Samuel Falvo II <sam.falvo at gmail.com> wrote:

> I could be talking out my rear; but, I'm willing to bet that if we had
> transistor-level control of the circuit, we could basically do
> whatever we wanted to achieve our speed goals.

At the cost of taking an eternity :P

AMD used to lay down some blocks like that (perhaps in big cores they
still do), but in Bobcat they moved to synthesized logic. Bigger and
slower, but much quicker to do, and was easily transferred to other

- Lauri

More information about the Libre-soc-dev mailing list