[Libre-soc-dev] Daily Kanban 2020aug10

[Luke Kenneth Casson Leighton]

yesterday:

* fixed a ton of combinatorial loops that were making FPGA compilation
difficult

today:

* started on reducing the size of the INT and FAST regfiles by merging some
of the ports.

currently, because there are 4 read and 2 write ports per INT reg, each 64
bit INT reg needs a THOUSAND gates, 400 of which are MUXes.

the way to reduce that is to share the ports between different pipelines.
this can be done by "grouping" pipeline input operands at the
PriorityPicker.

i have it partially working for read, except there is an obscure bug that
might be related to ALUCompUnit.  will investigate more tomorrow.

l.



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