[Libre-soc-dev] [OpenPOWER-HDL-Cores] libre-soc litex sim log

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Aug 6 16:41:04 BST 2020

On Thu, Aug 6, 2020 at 4:20 PM Timothy Pearson
<tpearson at raptorengineering.com> wrote:

> Nice work!

it's a big deal.  the LD/ST state machine interacting with the
Wishbone Bus was borked: one fix later and because of the significant
amount of individual pipeline unit testing and formal proofs, it just

interestingly, the LD/ST unit is entirely different from all other
units: it's not a pipeline at all, and is a rather complex FSM
(Out-of-Order machines cannot "fire-and-forget", unlike in-order ones:
they need a "Manager" which monitors any given operation all the way
from start to finish).  consequently LDST has had a lot less testing.

the next thing(s) to try out are running various microwatt unit test
binaries (and working out how to do that), compiling for a versa-ecp5
FPGA, running micropython and so on.

one thing in particular: the microwatt tests 0-100.bin, they run until
completion and only then is the results of the GPR extracted from the
debug log output and compared against "known good".  with the DMI
"register dump" now in place we can do *per-cycle* comparison of the
ongoing execution of microwatt binary tests, then compare against
libresoc execution.  if there are any problems we should be able to
pinpoint them immediately.


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