[Libre-soc-bugs] [Bug 1157] Implement poly1305

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1157

--- Comment #51 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Sadoon Albader from comment #49)
> (In reply to Luke Kenneth Casson Leighton from comment #48)
> > p.s. good progress :)
> 
> Thanks :)
> 
> I'm actually focusing on the add/mul part since it's the bulk of the work, I
> can deal with sv.dsrd later.
> 
> I've edited the python code a bit to show the full picture:
> 
>            
> d0=MUL(h0,r0);d=MUL(h1,s2);d0=ADD(d0,d);d=MUL(h2,s1);d0=ADD(d0,d);
>            
> d1=MUL(h0,r1);d=MUL(h1,r0);d1=ADD(d1,d);d=MUL(h2,s2);d1=ADD(d1,d);
>            
> d2=MUL(h0,r2);d=MUL(h1,r1);d2=ADD(d2,d);d=MUL(h2,r0);d2=ADD(d2,d);
> 
> The dependencies here only apply to add, meaning we can do 9 multiplications
> first in one go, and then add twice (assuming d here is a separate GPR for
> each multiplication).
> 
> Now, I was about to do this like I assumed in #19, but let's take a second
> look at this:
> 
> We have h0,h1,h2; r0,r1,r2; s1;s2
> 
> The multiplication occurs as follows:
> 
> d0 = h0r0 + h1s2 + h2s1
> d1 = h0r1 + h1r0 + h2s2
> d2 = h0r2 + h1r1 + h2r0
> 
> If we arrange the registers like this:
> [r2,r1,r0,s2,s1]
>  1  2  3  4  5
> We can do this:
> 
> setvl to 3
> sv.mul *RT, *h, *3
> sv.mul *RT, *h, *2
> sv.mul *RT, *h, *1
> 
> Perfectly reasonable, but I don't like this.

yep they are supposed to be covered by bigmul REMAP but
we really need the indices via svindex first, and then
can replicate them in bigmul-REMAP.

i *think* i have it, i did add modulo and i did add a "x+y"
mode so in theory it should be possible to produce

0  2  1
1  0  2
2  1  0 

> These muls can be one sv.mul if
> we arrange things correctly. I think we need svindex but am still trying to
> learn svindex and svremap.

remember you earlier made the mistake of confusing indices with values,
but then resolved that. looks like you need a refresher/reminder

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svindex.py;hb=HEAD

pay attention to lines 167, 169 and 181. run the unit test,
use print statements if you don't follow immediately ok?

the mapping system is a little awkward you have to remember that
SVSHAPEs 0-3 are *NOT* automagically connected up to registers.

that relationship is set by *svremap* which sets up the 5 possible
registers RA RB RC RT RS with the indices 0-3.

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