[Libre-soc-bugs] [Bug 1157] Implement poly1305

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1157

--- Comment #47 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Sadoon Albader from comment #46)
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=951586077f4bc63339a3e5e9b686dae715b87d73
> 
> Implemented first half of blocks in dsrd.

> ha! delighted to see!
> Made use of setvl as well except
> for dsrd but will use it for dsrd as well.

+                    'dsrd 11, 1, 3, 12',
+                    'dsrd 6, 0, 4, 13',
+                    'setvl 0, 0, 2, 0, 1, 1',

yes by moving r0 r1 and r6 and r11 you should be able to do

+                    'dsrd 6, 0, 3, 12',
+                    'dsrd 7, 1, 4, 13',

which becomes

+                    'setvl 0, 0, 2, 0, 1, 1',
+                    'sv.dsrd *6, *0, *3, *12',

interested to know what the rldiclr is about? what does it do?

btw you *may* have noticed this?

             h0 += t0 & 0xfffffffffff;
             h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff);
             h2 += (((t1 >> 24)             ) & 0x3ffffffffff) | hibit;

can become:

             h0 += (((t-1>> 0 ) | (t0 << 0 )) & 0xfffffffffff);
             h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff);
             h2 += (((t1 >> 24)             ) & 0x3ffffffffff) | hibit;

(where t-1 is deliberately set to zero)

therefore you can have *three* dsrds, set vl to *three* not two,
this should reduce by one instruction at least as you can set vl=3
just the once?

also..

+                    'sv.or *11, *11, *5',

should that just be

+                    'or 13, 13, 5'

assuming h0 is r11
         h1 is r12
         h2 is r13

?

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