[Libre-soc-bugs] [Bug 981] Support PowerPC ABI in cavatools

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 24 01:52:58 BST 2023


https://bugs.libre-soc.org/show_bug.cgi?id=981

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #20)

> 1. cavatools would be a challenging choice for us. It is RISCV-centric in
> the bad sense: it does not provide an opportunity to introduce other
> architectures there other than by extensively modifying the code.
> 2. The code quality leaves much to be desired.

these are not in any way fair statements to make, given the context, which
nobody knows about (as work should not have started at all on cavatools)

Peter Hsu, the author of this work, is the designer of the MIPS R8000
from 1994. the R8000 was extremely significant: it was able to
significantly outperform Cray Supercomputers at Sparse Matrix multiplication.

Peter retired only two years ago and cavatools was his last
main work during his employment at the Barcelona Supercomputing
Group where they had only money for RISC-V from the EU, despite
BSC wishing that they could develop Power ISA.

Peter very much wanted to add additional architectures but under
the time and budgetary pressure he could not do so. He was therefore
delighted to hear from me when I saw his ISC 2021 talk as I realised
the potential of cavatools as a high performance simulator.

Most of the planned platform-independent design work is therefore
*in his head*, and he also was pushed to add RISC-V RVV, before the
basic design was ready to have it added. This left him in the awkward
position, close to retirement, of having to short-cut much of the
plans he had for cavatools, which were that it be designed fully to
support multiple architectures.

Peter agreed to port to Power ISA if we got him the pieces that are
too complex for him to do: the Decoder and the Compiler. 50 "Forms"
in Power ISA instead of only 8. 214 instructions instead of 96.
He used parts of the riscv-spike simulator as a short-cut because
it was necessary, but it interfered both with the performance and
with the overall design.

the budget of bug #981 was *supposed* to be 100% exclusively for him to do
the Power ABI work, conditional on us providing him with the Power Decoder
and Compiler.

nobody - none of us - were supposed to touch not even one single line of
cavatools. that work was for Peter Hsu to carry out, as he is its author and
he is the one that knows it best and how it fits together.

I was not able to tell anyone any of this, because work started without me
being consulted on the context and background of how to go about completing
this complex task within the very small budget and time available to us.

this role of finding creative solutions to complex problems is what I am
good at. i know *instinctively* how to cut corners by finding the right
people and the right pieces, but if any of you attempt to rush ahead without
consulting me first, or do work without listening to what I am saying (because
you think i am "ordering you about") then the project will simply fail.

fortunately enough of the bug #982 task has been completed such that with
a little more work it will be possible to justify putting the budget of
bug #981 onto ISACaller, because it works TOWARDS cavatools.

but i cannot in any way justify signing off a rate of EUR 4,500 per day
when the agreed rate as approved by the EU Independent External Reviewers
is EUR 3,000 a month.  the difference of 50x higher is just too great.

if however work on ISACaller ABI support continues *here* for a few
more days, such that more information is available to make a better
new cavatools grant, that is perfect.

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