[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|shriya.sharma at redsemiconduc |andrey at technepisteme.xyz
                   |tor.com                     |
                 CC|                            |shriya.sharma at redsemiconduc
                   |                            |tor.com

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)

> * TODO: tidy up the corrections to the wiki page

Andrey you need to sort out the corrections made,
read them, tidy them up, and generally get a better
understanding and appreciation that there has been an
InOrder core in soc/ for over 12 months, and provide
links to it that demonstrate that you know this.

as written the page gave the false impression to the
wider world that the InOrder Core was nonexistent,
which is quite serious from the perspective of NLnet
funding and promotion of the EU's trust in NLnet,
and much more besides.

you can find the commit history outlining the corrections
that were made which you need to tidy up, here:

https://git.libre-soc.org/?p=libreriscv.git;a=history;f=3d_gpu/architecture/inorder_model.mdwn;h=e61c7a938eac023889ff579018a374746e18f4c7;hb=773391b0eb427c9d61bef169c8583c9922a1f417

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