[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=982

--- Comment #133 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
dmitry just so you know (i will look at this tomorrow):

  11 * sc LEV
  12 
  13 Pseudo-code:
  14 
  15     SRR0 <-iea CIA + 4
  16     SRR1[33:36] <- 0
  17     SRR1[42:47] <- 0
  18     SRR1[0:32]  <- MSR[0:32]
  19     SRR1[37:41] <- MSR[37:41]
  20     SRR1[48:63] <- MSR[48:63]
  21     TRAP(0xC00)  <<<<--- this ACTUALLY calls ISACaller.TRAP(0xc00)

which you will find at... errr.... here:

1318     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
1319         """TRAP> saves PC, MSR (and TODO SVSTATE), and updates MSR
1320 ...
     ...
     ....
1339         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1

so yes, this is why you should find that SRR1[PIb.TRAP] has been set to 1
because that's what ISACaller.TRAP() does. whether that is the right
thing to do, if you *really* want to look at Power ISA spec around page
1070 the interrupt tables and behaviours please feel free but no bonus
points given for doing so :)

-- 
You are receiving this mail because:
You are on the CC list for the bug.