[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=982

--- Comment #119 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #117)
> I still had to make it somewhat more complex, because self.call will not do
> anything, only `yield from self.call` will. Also, since basically our insn
> flow is unchanged, but we have to "inject" rfid instruction, I had to be
> somewhat creative.
> 
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=cea6b00e0cfb2acca2098794ad70c04d0d53cb29

ok you notice how in comment #90 i did *not* pass in the "cheat"
argument? that was deliberate. it means that the straight rfid
pseudocode gets called, as-is.

redirecting hrfid to rfid will break hrfid when it is implemented,
that should definitely not be done.


> I also had to introduce a way to pass initial_msr parameter into test_runner.

ah this is not a surprise

> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=e25fca65a5a0faecdd9040689b5fe1f44b9a64a7

pass in "None" instead and do "if initial_msr is None:
initial_msr=0x9000000000001" (MSR.LE | MSR.SF)

> One this is done, almost everything works, except MSR check:
> 
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=dfec8c6456adfd3690d5d8da5a78fe3aa6c96b66

aaawesome.

okaay so now that value 0xfffffeeeablahblah that can be the expected
e.msr!

and with the removal of the redirection of hrfid we are done!

(In reply to Dmitry Selyutin from comment #118)
> If I understand correctly, we must introduce some code residing at 0xc00,

noo: the call to self.syscall *is* the [kernel/OS] code at 0xc00!
(and yes that kernel/OS code as its last instruction includes an
rfid, hence why we have to explicitly call both sc and rfid)

> FTR, here's what I get for MSR mismatch:
>   File "./src/openpower/decoder/isa/test_syscall.py", line 23, in
> run_tst_program
>     self.assertEqual(sim.msr, 0xffffffffffffffff)         # MSR changed to
> this by sc/trap
> SelectableInt(value=0xfbfffffefd7f10c5, bits=64) != 18446744073709551615

great! see comment #90 again (2nd from last paragraph).
set e.msr = 0xfbfffffefd7f10c5 and we are pretty much done.

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