[Libre-soc-bugs] [Bug 1157] Implement poly1305

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1157

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|konstantinos at vectorcamp.gr  |shriya.sharma at redsemiconduc
                   |                            |tor.com

--- Comment #42 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c89f618a57b299169e1bcbe4a342278247ad2ce5

looks good sadoon. first sv instructions!


+                'or 11, 9, 9', # move t0 to r11
+                'rldicl 20, 9,  %d, 44' %(64-44), # equivelant to srdi
+                'rldicr 21, 10, 20, %d' %(63-20), # equivelant to sldi
+                'or 12, 20, 21', # move result to r12, 20&21 are temps
+                'rldicl 13, 10, %d, 24' %(64-24),
+                'or 13, 13, 30', # to accommodate hibit

convert those to *scalar* dsrd. comment #18.
do *not* attempt to go straight to svp64.

incremental.

replace with *scalar* first.

then go, "huh. these two dsrd instructions are using sequentially-
incrementing registers. hey i know, that means i can put "sv." in
front and use only one instruction!"

notice how i did *not* say "go straight to something complex that
you have never used before and do everything at once"?

8ncremental steps, incremental steps, incremental steps.

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